RISC-V 64GCV C910*4@1.85 GHz Each core contains 64KB I cache amd 64KB D Cache 1 MB of Shared L2 Cache Support TEE and REE, configured during core booting Support multi-core debugging framework of custom and RISC-V compatible interface Independent power domain, supports DVFS
Graphics
Graphics
OpenCL 1.1/1.2/2.0 OpenGL ES 3.0/3.1/3.2 Vulkan 1.1/1.2 Android NN HAL
Connectivity
Networking
2x Gigabit PHY
Other
NPU
Support 4 TOPS@INT8, up to 1 GHz Support TensorFlow, ONNX, Caffe Support CNN, RNN, DNN
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